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This is a comparison of ARM instruction set architecture application processor cores designed by Arm Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R , ARM Cortex-M , or legacy ARM cores.
The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. [1] It was introduced in 2007. [ 2 ]
The ARM Cortex-A is a group of 32-bit and 64-bit RISC ARM processor cores licensed by Arm Holdings.The cores are intended for application use. The group consists of 32-bit only cores: ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Cortex-A17 MPCore, and ARM Cortex-A32, 32/64-bit mixed operation cores: ARM Cortex-A35, ARM Cortex-A53, ARM Cortex ...
ARM7, ARM Cortex-M, ARM Cortex-A (on Jailhouse hypervisor), Hitachi H8, Altera Nios2, Microchip dsPIC (including dsPIC30, dsPIC33, and PIC24), Microchip PIC32, ST Microelectronics ST10, Infineon C167, Infineon Tricore, Freescale PPC e200 (MPC 56xx) (including PPC e200 z0, z6, z7), Freescale S12XS, EnSilica eSi-RISC, AVR, Lattice Mico32, MSP430 ...
ARM Cortex-A8: 2005 13 Dual-issue, in-order, speculative execution, superscalar, 2-way pipeline decode ARM Cortex-A9 MPCore: 2007 8–11 Out-of-order, speculative issue, superscalar ARM Cortex-A15 MPCore: 2010 15 Multi-core (up to 16), out-of-order, speculative issue, 3-way superscalar ARM Cortex-A53: 2012 Partial dual-issue, in-order ARM ...
Cortex-A8: Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline 16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZone Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz) [40] Cortex-A9